The present invention relates to flash memory, and in particular to flash storage devices that include a flash controller.
Flash memory has become a popular non-volatile memory for a variety of applications, because it offers a superior cost-performance ratio. The well-known drawback of flash memory is its error rate, which is customarily overcome by adding a flash controller that is programmed to manage error correction. Thus, when a sector of data is written onto the flash memory, an additional amount of information, calculated with respect to the content of the data sector, is added, to allow recovery from errors. Using typical error-correction algorithms, 6 bytes of such extra data, called ‘error correction code’ (ECC), allows recovery from two faulty bits within a 512-byte sector. Then it is common to run all data read from a flash memory through the flash controller to identify and correct errors. Usually, errors are not just corrected on their way from the controller toward a target device, but the corrected data is also written back onto the flash memory to restrain the accumulation of errors.
Checking and correcting all data read from a flash memory is critical for many applications, but also slows down the data transfer process, because of the extra processing done by the flash controller. It is therefore desirable to find a method and design to reduce this extra delay to a minimum, without compromising the quality of error correction.